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<div class="title">xv_hdmirx_hw.h File Reference</div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__hdmirx_8h.html" title="This is the main header file for Xilinx HDMI RX core. ">xv_hdmirx.h</a> file.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
----- ------ -------- --------------------------------------------------
1.0   gm, mg 11/03/15 Initial release.
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:ab1245a8a62b2b5611cc4cbb2aa4af75b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#ab1245a8a62b2b5611cc4cbb2aa4af75b">XV_HdmiRx_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#ac1f9ae7bd366a3fe5db4faa53b58e4af">XV_HdmiRx_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="separator:ab1245a8a62b2b5611cc4cbb2aa4af75b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a407dbf36f2752c30d265e3a8a25d29fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx__hw_8h.html#a407dbf36f2752c30d265e3a8a25d29fe">XV_HdmiRx_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#aed43ceb241150a4219514143f8473a4d">XV_HdmiRx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="separator:a407dbf36f2752c30d265e3a8a25d29fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ab9b4d72b50e6d6bfb3d5a570c8d172b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a87eaa7535d04479ccecaec7a1a97aadc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="add5a4bf9070b2decf5ac41ca31a4e914"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a567c57fe4410dd785a044d5bc5ffd55b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a9428f4a8196d2f0576ba5ea841037f6b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a3f83199b3cdb183ee02353d031743062"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_CTS_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD CTS Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ae3dcd032d351867697f19280fdeb1eeb">XV_HdmiRx_GetAcrCts()</a>.</p>

</div>
</div>
<a class="anchor" id="aa27e0e3487532f0476be811b7d95e799"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a0c222588615d7174edf1b8c474675ec3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_N_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD N Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a0b9483d540e72c619bcc9ba5d516ebe8">XV_HdmiRx_GetAcrN()</a>.</p>

</div>
</div>
<a class="anchor" id="a9d187ed36cde3cb36eeae049ad3d91f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_ACT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a98ca2ff777b73ff293379306f5f57b8e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_ACT_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Active mask. </p>

</div>
</div>
<a class="anchor" id="a292e4fe82c8bbaecd8e3a0982762d557"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_CH_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio channel mask. </p>

</div>
</div>
<a class="anchor" id="a4a7eab9bd6be6a6ba673e6f5a959dea7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_CH_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio channel Shift. </p>

</div>
</div>
<a class="anchor" id="ad4a1038421efd5ff07accc769019102e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_FMT_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio Format mask. </p>

</div>
</div>
<a class="anchor" id="a7896f888d03cc5cd46c5c869ccfc5421"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_AUD_FMT_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio Format Shift. </p>

</div>
</div>
<a class="anchor" id="ab307264da6388cded12f39f3c7a24732"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_CH_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a95678b96a69da93e8ed300c4d8e75475"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="aaeabc64551cfb1c8e0b4451fe5b4bdaf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUD_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUD_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a3a6b7a9edc5ba9bed414a654b4a92cf3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="ab1b73383c2d1aa43815eb0431f3016df"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a1d5dd828751e58c1acd0efa6cb37cf63"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a0b8f81778779480d71ed771ec5a98610"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Run mask. </p>

</div>
</div>
<a class="anchor" id="ae1e6cac9e393cbaa0fff3c768e05a6ce"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="ac80a617f8a5b2b43b099c0b500578b32"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_DAT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Data Register offset. </p>

</div>
</div>
<a class="anchor" id="aa81442ef4d9a2c67d81e27b171524741"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a18c0b376a593da7df6775ebc78394355"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_CS_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI colorspace mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="ac299e0cc30499f86f60267f7c23d3242"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_CS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI colorspace Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="a2a2964d1f987bbdb5055dc4afeb66c0a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI infoframe mask. </p>

</div>
</div>
<a class="anchor" id="aae57be2d73942a73e349d3d468d4f8b7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_VIC_MASK&#160;&#160;&#160;0x7F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI VIC mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>.</p>

</div>
</div>
<a class="anchor" id="a1eac59ae54921281d77742aabb932158"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_AVI_VIC_SHIFT&#160;&#160;&#160;18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI VIC Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>.</p>

</div>
</div>
<a class="anchor" id="ae26445a2639c20903f9dd19eded90014"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_FIFO_EP_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Empty mask. </p>

</div>
</div>
<a class="anchor" id="a031ed61017975ae43a74b82e80a499a3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_FIFO_FL_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Full mask. </p>

</div>
</div>
<a class="anchor" id="a2e4a698c7fee38a5e5a92cc9530c1c1a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_AVMUTE_MASK&#160;&#160;&#160;(1&lt;&lt;31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP avmute mask. </p>

</div>
</div>
<a class="anchor" id="a6e84a7312408ad6204ee0846573e292c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_CD_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP colordepth mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="a6078073cb572492cffb23b1c85a514a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_CD_SHIFT&#160;&#160;&#160;26</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP colordepth Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="a6968421b806da48906fe3e766f3d0cc4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status General control packet mask. </p>

</div>
</div>
<a class="anchor" id="a9b1f3886f6d42a5d5b69a1851c77b1ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_PP_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP pixel phase mask. </p>

</div>
</div>
<a class="anchor" id="af6f919dfe8242811589c914bb008a3e9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_GCP_PP_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP pixel phase Shift. </p>

</div>
</div>
<a class="anchor" id="aeb2ba5951bb5bc0f1db1840deac5652f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="addf6d2a2c6904375b30d86097b2818f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_NEW_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packet mask. </p>

</div>
</div>
<a class="anchor" id="ab0a13f1e1dec574124a7988bb34ca627"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_NEW_PKTS_MASK&#160;&#160;&#160;0x1F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packets mask. </p>

</div>
</div>
<a class="anchor" id="a7a57a0928c7a74d34dc804de668d28cd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_NEW_PKTS_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packets Shift. </p>

</div>
</div>
<a class="anchor" id="a73d86d2cff54ce9143501c9029b6666e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_AUX_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_AUX_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>, <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>, <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>, and <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ac5fcd5ad68b451baf56e90de899e7ede"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a92855dc688a9f79d080f1eab92e17144"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_EDID_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control EDID enable mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a937baab4a62131f510e87602c5e5f669"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_HDCP_EN_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control HDCP enable mask. </p>

</div>
</div>
<a class="anchor" id="acda38629aa70cc313c59ba64eb8e3318"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Interrupt enable mask. </p>

</div>
</div>
<a class="anchor" id="a7a103df1d10146f4676b28638b418bca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a91f5315d7efd6486cef6ed81161c1411"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a2fcc95a6129eacc331e014e496db9031"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_SCDC_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control SCDC clear mask. </p>

</div>
</div>
<a class="anchor" id="a70913fe092b1adef31afb152cd679de3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_SCDC_EN_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control SCDC enable mask. </p>

</div>
</div>
<a class="anchor" id="a8272d8237c5560511743f6645351c889"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a87d82ea13dd71da7ed87b4645b056dd5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_DATA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID data offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a8b682b85fe84e6b981cd441bc1e737c1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_RP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID read pointer offset. </p>

</div>
</div>
<a class="anchor" id="a659ddc496ff647b94aab4c2e401eb131"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_SP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID segment pointer offset. </p>

</div>
</div>
<a class="anchor" id="abd5e2bee6eb83de864de63600afef44d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_EDID_WP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID write pointer offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a6b100412180e030ef95cb8ecaa5934b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_HDCP_ADDRESS_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read HDCP address offset. </p>

</div>
</div>
<a class="anchor" id="acc2e9a9d6af18df813b60237a319900a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_HDCP_DATA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read HDCP data offset. </p>

</div>
</div>
<a class="anchor" id="ad73e990f64f6dd2501e19b8ec873f26a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="aeb8c90015c1fe7b50a3c5707aad8c259"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_BUSY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

</div>
</div>
<a class="anchor" id="af604d47ae26f7f564092cf94e9cb85d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_EDID_WORDS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status EDID words shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8c.html#a0ede81f7ab3357d5fe81c8df0f125e27">XV_HdmiRx_DdcGetEdidWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a6ea0539a870ea8cf811427f6161820aa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a16b2cc4ca12f9a1febab4e8ac6bfded4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_RD_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP read event mask. </p>

</div>
</div>
<a class="anchor" id="a32c6b46244beb84318d27c16b5fd8d99"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_HDCP_WR_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP write event mask. </p>

</div>
</div>
<a class="anchor" id="aeacfe034e74301f0f50846e09966266f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a2549440290b1505f595c0986c5fe6f13"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_DDC_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8c.html#a0ede81f7ab3357d5fe81c8df0f125e27">XV_HdmiRx_DdcGetEdidWords()</a>, and <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a343d84b77859271fd326e2e8e8050fcd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_SCL_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status state of the SCL input mask. </p>

</div>
</div>
<a class="anchor" id="af2cb844892744258e47f631cc8f1ef59"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_DDC_STA_SDA_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status state of the SDA input mask. </p>

</div>
</div>
<a class="anchor" id="ab35e8d251d6f95ff5b39b18eb7b3ef03"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="ac1f9ae7bd366a3fe5db4faa53b58e4af"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="abc673f54db2a25dee45c4f1c8d321e95"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="aa6d26913bac16d95ae5a5af1173ccb13"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_ERR_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Error Clear mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="ab0f62d22721883dd2d740b4edbf6872a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a81049dffe0990151a58b1728dade86f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a9be02907eee90b0290839d85acc6818c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Run mask. </p>

</div>
</div>
<a class="anchor" id="aa310321ea49ca6efcd3cd727554d74df"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a940806715e55ccfd0f0813e1b64abd3d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="afb0995c7dadd967e0be16f4d31d60bd8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_LNK_ERR0_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 0 Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#aad02ea3d99f0ac3a7f4a0b18f88d62e8">XV_HdmiRx_GetLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a06437de32dc8a09506cd5513a8fc66ac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_LNK_ERR1_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 1 Register offset. </p>

</div>
</div>
<a class="anchor" id="a65b7bcbf5858f0f7786c8ca1322eb33e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_LNK_ERR2_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 2 Register offset. </p>

</div>
</div>
<a class="anchor" id="a6b68f41c0790de0b711903449a1286b2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_STA_ERR_MAX_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Maximum Errors mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a70bb5419e7285a268518668fda1d70cd">XV_HdmiRx_IsLinkStatusErrMax()</a>.</p>

</div>
</div>
<a class="anchor" id="af50dcf2fedf4c2d07147f47e4bb64037"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a99d2e4c21738838bb3de9ab7042019b1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_LNKSTA_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_LNKSTA_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>, and <a class="el" href="xv__hdmirx_8h.html#a70bb5419e7285a268518668fda1d70cd">XV_HdmiRx_IsLinkStatusErrMax()</a>.</p>

</div>
</div>
<a class="anchor" id="a4a6303e5aa23e44351563d3559d9a7cc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_MASK_16&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 bit mask value </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="aed43ceb241150a4219514143f8473a4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="afd049a051639c6315d1da85f2c96e1db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a6bda9bcf1d7cf49a93827bf03eea2e4a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a1687fd8119ecce7ab4096ff398ba0bb7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control register offset. </p>

</div>
</div>
<a class="anchor" id="a7b7db301fdc44d8f8252475ed22f6c2f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a489d5aaf485199c1eedcbfea6f4c68ec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a3b2aba60044d1ec3e9ddfc0172f77141"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_ID&#160;&#160;&#160;0x2200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO ID. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a3072b2f474e183f436eceb634d67a7cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Identification register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="aac130c5fe1e9b758f5461b5ef6cd6d22"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_DET_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In cable detect mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ae971e0400e365b9f192a1fa190a4b0fd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_EVT_FE_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Falling Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ab31f69e47fbb9567a8f3f1d1c296899b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_EVT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Register offset. </p>

</div>
</div>
<a class="anchor" id="add0c5bcaa9260b976d6ad1b020d59d8a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_EVT_RE_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Rising Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a7f6d5c17336a530b92869fa191b8cc8f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_LNK_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In link ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="af32e3df9ebde480b8a20e03ec37a03eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Mode mask. </p>

</div>
</div>
<a class="anchor" id="a729bb6c385b324610317135c52298eba"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a36bca352ee91492da1392cae5ddcfa6c">XV_HdmiRx_GetTmdsClockRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="a63a6b5dcd3cd49bbc464bc67f3ad36cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCDC_SCRAMBLER_ENABLE_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In SCDC scrambler enable mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="af439412374d6713f5b5a375c54d9df68"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In SCDC TMDS clock ratio mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx_8h.html#a36bca352ee91492da1392cae5ddcfa6c">XV_HdmiRx_GetTmdsClockRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="a257587f5ad87dd0795d3891d3fda3ac6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK0_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 0 mask. </p>

</div>
</div>
<a class="anchor" id="abf5edbd5735e21545ab367940bb59aa3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK1_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 1 mask. </p>

</div>
</div>
<a class="anchor" id="a28904b530f07081146e224cc033c3cdb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_SCRAMBLER_LOCK2_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 2 mask. </p>

</div>
</div>
<a class="anchor" id="a477171cef5c2a0b4621facbb41b82eb8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_IN_VID_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In video ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a80d63952308a1e96d3bfd10db732b94c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a03f17ccc9e2953ac921f07446dfc9c16"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_COLOR_SPACE_MASK&#160;&#160;&#160;0xC00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a5c1716813413cd8ca952fafe0520b782"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_COLOR_SPACE_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="aaa2244687e75ef859bf959aade976488"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_DEEP_COLOR_MASK&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Deep Color mask. </p>

</div>
</div>
<a class="anchor" id="ab370f0d9a89642724e7a1ad311468aff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_DEEP_COLOR_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Deep Color shift. </p>

</div>
</div>
<a class="anchor" id="a51974eaab5f1447924b24e7ad9795f41"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_HPD_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Hot-Plug Detect mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="aebf168954f7f549697220cb79a2db0e5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_LNK_EN_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out video enable mask. </p>

</div>
</div>
<a class="anchor" id="a7e3ed781e3e5bc38c206ee7d712894c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_MSK_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Mask Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>, and <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a21ac38c5488361502fc525c6497e922b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>, and <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a415a6510fe5c6bc29230e9c370e13985"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_PIXEL_RATE_MASK&#160;&#160;&#160;0xC0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a93050e6b1ea95d7147823e81113e6919"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_PIXEL_RATE_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="ae9ededc60f434b8f94a94138d0ae1770"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_RESET_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Reset mask. </p>

</div>
</div>
<a class="anchor" id="ad392d4b85c6851c8ab14735efbfb863c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SAMPLE_RATE_MASK&#160;&#160;&#160;0x300</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate mask. </p>

</div>
</div>
<a class="anchor" id="ab7a79de3656d1b5fcaf1143c9a8ddd4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SAMPLE_RATE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate shift. </p>

</div>
</div>
<a class="anchor" id="a923b78bca6113c26d4c9aa2450e12d31"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SCRM_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Scrambler mask. </p>

</div>
</div>
<a class="anchor" id="add1b42f293960a225e7c7addc81ba41a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a5461b9268a85702c01115f85b1e49537"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_OUT_VID_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out video enable mask. </p>

</div>
</div>
<a class="anchor" id="ada79d92307e4e82afb7e7e0e477bdb8c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Event mask. </p>

</div>
</div>
<a class="anchor" id="abd3c33cf8c70cbeb50a95f7d58556579"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="af1fe9c13a0a5c613a4ca868c82c6f969"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_PIO_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_PIO_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ab1245a8a62b2b5611cc4cbb2aa4af75b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#ac1f9ae7bd366a3fe5db4faa53b58e4af">XV_HdmiRx_In32</a>((BaseAddress) + ((u32)RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a HDMI RX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmirx__hw_8h.html#ab1245a8a62b2b5611cc4cbb2aa4af75b" title="This macro reads a value from a HDMI RX register. ">XV_HdmiRx_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>, <a class="el" href="xv__hdmirx_8c.html#a0ede81f7ab3357d5fe81c8df0f125e27">XV_HdmiRx_DdcGetEdidWords()</a>, <a class="el" href="xv__hdmirx_8h.html#ae3dcd032d351867697f19280fdeb1eeb">XV_HdmiRx_GetAcrCts()</a>, <a class="el" href="xv__hdmirx_8h.html#a0b9483d540e72c619bcc9ba5d516ebe8">XV_HdmiRx_GetAcrN()</a>, <a class="el" href="xv__hdmirx_8h.html#a4b2650f744a2a244482124697e632863">XV_HdmiRx_GetAviColorSpace()</a>, <a class="el" href="xv__hdmirx_8h.html#afaa89bbc453b2d7e1446140c73b7baee">XV_HdmiRx_GetAviVic()</a>, <a class="el" href="xv__hdmirx_8h.html#a87e0904b6a6167f3cde2e7fcc0843e1d">XV_HdmiRx_GetGcpColorDepth()</a>, <a class="el" href="xv__hdmirx_8h.html#aad02ea3d99f0ac3a7f4a0b18f88d62e8">XV_HdmiRx_GetLinkStatus()</a>, <a class="el" href="xv__hdmirx_8h.html#a36bca352ee91492da1392cae5ddcfa6c">XV_HdmiRx_GetTmdsClockRatio()</a>, <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>, <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>, <a class="el" href="xv__hdmirx_8h.html#a70bb5419e7285a268518668fda1d70cd">XV_HdmiRx_IsLinkStatusErrMax()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a58ff62ffa6d07e198733b7ef576f2ac3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_SHIFT_16&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 shift value </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx__selftest_8c.html#a6b25b29eebf53f7084b6a154ad89a66f">XV_HdmiRx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="acc84ec76d1d4480d32bfcc0a6d36c9cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Counter Register offset. </p>

</div>
</div>
<a class="anchor" id="a418a4e82c61dfecb6fba2ae6fa645cc5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a32d7a633d71248f00c6c3a0c4cc45709"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="aadd3b41587950a820be6cdacc340bef3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control register offset. </p>

</div>
</div>
<a class="anchor" id="a1583ebb7279d885effb9fcdd993210fd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Run mask. </p>

</div>
</div>
<a class="anchor" id="acfb602db80f1b5565752761a4e1d3203"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a0cf543f243de78f481f48c4639ac1f94"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Identification register offset. </p>

</div>
</div>
<a class="anchor" id="a8561f573c1afd06984ecd2fc0c3ffd3b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_STA_CNT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status counter Event mask. </p>

</div>
</div>
<a class="anchor" id="aa15bfe16e6a4aa77cc680ea22cd03c9c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a8a2a11c35b8b89348b193ce2273b0044"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_TMR_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_TMR_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a03680168612106285110985639ce8aaf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VER_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VER_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a09dd02e2eec9abeece66f495f3f1624d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VER_VERSION_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VER_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Version Register * offset. </p>

</div>
</div>
<a class="anchor" id="a8e1330cc6542ff96733cb7f7e29465fc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_ACT_LIN_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Active Lines Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a680b488ede6d6a8ec9d730deff7559e8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_ACT_PIX_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Active Pixels Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="acbbb7da3f11adf6adaeb53543411f7b2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Clear Register offset. </p>

</div>
</div>
<a class="anchor" id="a79e70fa96e30594b7f96286c786a8ab6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_FIELD_POL_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control field polarity mask. </p>

</div>
</div>
<a class="anchor" id="a742400164fe40d8d72d309affc8d2bf2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="acc56d3a8152c535ce8783d2ff82f4227"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Register offset. </p>

</div>
</div>
<a class="anchor" id="af9e3cef6d874c106289bb83133776baf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Run mask. </p>

</div>
</div>
<a class="anchor" id="af82aee3a907bcd6e34308267e8d67014"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Set Register offset. </p>

</div>
</div>
<a class="anchor" id="afb38982d65ef42bbd7c4e16cef5cf43d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_THRESHOLD_MASK&#160;&#160;&#160;0xff</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control threshold mask. </p>

</div>
</div>
<a class="anchor" id="a3c6c478965654e7c31dfaa3ab99e4033"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_CTRL_THRESHOLD_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control threshold shift. </p>

</div>
</div>
<a class="anchor" id="ae639e59a8ebf41da214a1de1246feae3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_HBP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(14*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Back Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a9d1c2a6712699269f8e69dd2c576a3eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_HFP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Front Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a18b3fcc81e0b4ebffe5d03b93b9e3a92"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_HSW_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Sync Width Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a1962a0c3c80aa477e98f25e99aeae0d7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a8810fe79655104c0b273b6868b2407fb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_STA_FMT_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Format mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="abb3320c46658b4aaa9faa3c78f535fd1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_STA_HS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Hsync Polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="aeb5ef898fca55fa90ee72374af67f0ae"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX_VTD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
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<p>VTD Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

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          <td class="memname">#define XV_HDMIRX_VTD_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(4*4))</td>
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<p>VTD Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>, and <a class="el" href="xv__hdmirx__intr_8c.html#a1af2b06988bf558daf78a4ffb7df8838">XV_HdmiRx_IntrHandler()</a>.</p>

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          <td class="memname">#define XV_HDMIRX_VTD_STA_TPR_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
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<p>VTD Status timing parameter ready event mask. </p>

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<a class="anchor" id="aa003ad3deba710d8250e4d09c3d706a4"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_STA_VS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
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<p>VTD Status Vsync Polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a760c24aa9d33dd2727c6106537c4723d"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_TOT_LIN_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(7*4))</td>
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<p>VTD Total Lines Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="ada7dd9b96b61f5400488120a035a733c"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_TOT_PIX_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(5*4))</td>
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<p>VTD Total Pixels Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a0f25a70ae387411851a4e26d62c4a42a"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_VBP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(12*4))</td>
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<p>VTD Vertical Back Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a7976bef95da52ceaf075d949bbf95fe4"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_VFP_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(11*4))</td>
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<p>VTD Vertical Front Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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<a class="anchor" id="a38aa5d3cc486342d8414cccece29d578"></a>
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          <td class="memname">#define XV_HDMIRX_VTD_VSW_OFFSET&#160;&#160;&#160;((XV_HDMIRX_VTD_BASE)+(9*4))</td>
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<p>VTD Vertical Sync Width Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a9e11e21cff30c73785c0a2f63944ccd0">XV_HdmiRx_GetVideoTiming()</a>.</p>

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          <td class="memname">#define XV_HdmiRx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmirx__hw_8h.html#aed43ceb241150a4219514143f8473a4d">XV_HdmiRx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td>
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<p>This macro writes a value to a HDMI RX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx__hw_8h.html#a407dbf36f2752c30d265e3a8a25d29fe" title="This macro writes a value to a HDMI RX register. ">XV_HdmiRx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx_8h.html#a8fd540843fe61be0545034a56ebdb3d9">XV_HdmiRx_CfgInitialize()</a>, <a class="el" href="xv__hdmirx_8h.html#ac1b7e27bd3874e33114b2e0210f54d4c">XV_HdmiRx_ClearLinkStatus()</a>, <a class="el" href="xv__hdmirx_8h.html#a15aff8e40535d72186c05dcdd2e5aa93">XV_HdmiRx_DdcLoadEdid()</a>, <a class="el" href="xv__hdmirx_8h.html#a72457c11b43becc2fd5bffc1b748bf30">XV_HdmiRx_SetColorFormat()</a>, <a class="el" href="xv__hdmirx_8h.html#a8601d159dffdd4fd77d05d248b366a54">XV_HdmiRx_SetHpd()</a>, and <a class="el" href="xv__hdmirx_8h.html#ab48ac8ab5eeddd6197c6220db1ac8ee5">XV_HdmiRx_SetPixelRate()</a>.</p>

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